Suman Bhat R
Design Verification Engineer at Intel
- Role
- Design Verification Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Suman Bhat R
8+ Years of Experience in VLSI Design Verification- SoC Verification- RTL and Gate Level Simulation- Silicon BringupSpecialties- System Verilog - OOPs Concepts, Assertion, Functional Coverage- Methodologies - UVM- AMBA - APB, AHB,AXI
Experience
Design Verification Engineer
Aug 2022 — Present · Bengaluru, IN
Education
Malnad College Of Engineering
Bachelor of Engineering (BE)
2008 — 2012
Skills
- Amba Ahb
- Jtag
- C++
- Perl
- Uvm
- C
- Vlsi
- Soc
- Vhdl
- Systemverilog
- Rtl Design
- Functional Verification
- Tic
- Linux
- Verilog
- Debugging
- Gate Level Simulation
- Clearcase
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