Suleman Nadaf

About Suleman Nadaf

I am a graduate from University of Minnesota - Twin cities with major in Electrical and Computer Engineering (focus on VLSI design and Computer architecture). I am currently working as CPU DV Engineer at Apple Inc, Austin, TX. Prior to this, I have interned at Apple Inc, Austin, Texas as CPU Design Verification Intern. I have also worked on IP Verification (RTL level) in ARM for 2 years. My areas of interest include Microarchitecture, Design Verification, System Verilog(UVM), Formal Verification. I have hands-on experience in synthesizable testbench design, development of transactors, system Verilog checkers required for DV. In addition to that, I have experience with development of automation framework using Perl/Python/Shell scripting.Skill set- Tools: Synopsys Design Compiler/VCS/DVE, Modelsim, Mentor Graphics tools Questasim/Veloce, Cadence ncsim/incisive- Formal Verification: Jaspergold- Programming and scripting: UVM, System Verilog, Verilog, C++, C, Python, Perl, Shell scripting, TCL- Operating system : Linux/Unix, Windows- Database: SQLite- Packages: MATLAB, Eclipse, LABView, Mathematica- RTL stitching: ARM-Socrates Weaver, AMBA Designer- Protocols: AMBA Protocols(APB, AXI, ACE, ACE-Lite, CHI-E), DDR3/DDR4- Architectural Simulators: Multi2sim, DRAMSIM, Ramulator : n•••••••@umn.edu

Experience

1. Cpu Design Verification Engineer

   Apple

   Jun 2018 — Present · Austin, TX, US

Education

• University of Minnesota

  Master’s Degree, Electrical and Electronics Engineering

  2016 — 2018

• RV College Of Engineering

  Bachelor’s Degree, Electronics and Communication Engineering

  2010 — 2014

Skills

• Cadence Virtuoso
• Debugging
• Python
• System Architecture
• Perl
• Embedded Systems
• Logic Design
• Perl Automation
• Labview
• Scripting
• Arm Assembly
• Universal Verification Methodology (Uvm)
• Matlab
• Arm Architecture
• Microsoft Word
• Microcontrollers
• C
• Programming
• Vhdl
• Simulations
• System on a Chip (Soc)
• Arm Cortex-a
• Shell Scripting
• Systemverilog
• Spice
• Testing
• Rtl Design
• Microsoft Excel
• Powerpoint
• Microsoft Office
• Computer Architecture
• Windows
• Eclipse
• C++
• Soc
• Verilog
• Semiconductors
• Linux
• Modelsim
• Very-Large-Scale Integration (Vlsi)