Suleman Khan

About Suleman Khan

I am a Senior ASIC / ESD Verification and Design Automation Engineer with 13+ years of experience spanning Cadence, Xilinx (AMD), and Infosys, specializing in ESD PERC methodologies, Pegasus & Calibre sign-off, and advanced-node tapeouts.I have supported successful customer tapeouts across leading foundries including TSMC, Samsung, and GlobalFoundries, working on nodes such as N3, N2, N7, N16, S5, S4, and GF12LP. My expertise covers schematic and layout ESD PERC, DRC/LVS/ERC, in-design verification, and custom rule deck development.At Cadence, I work closely with global customers to enable first-time-right tapeouts using Pegasus, supporting both sign-off and in-design flows, and collaborating with R&D to improve tool capabilities. I have also conducted Pegasus PERC training, developed RAKs, and presented at ARM Global Tech Summit 2024.Previously at Xilinx, I architected ESD verification methodologies for product and DDR5 test chips in TSMC 7nm, contributed to BRAM/URAM/FEC layout and physical verification, and built multiple automation flows using SKILL and PERL to significantly improve design productivity.I enjoy solving complex verification problems, building scalable automation, and working at the intersection of technology, tools, and customer success.

Experience

1. Principal Product Engineer

   Cadence

   Jun 2024 — Present · Bengaluru, IN

Education

• G.M Institute Of Technology , Davangere , Karnataka

  Bachelor Of Engineering, Electronics and Communication

  2007 — 2011

• GM Institute of Technology

  Bachelor of Engineering - BE, Electrical, Electronics and Communications Engineering

Skills

• Synopsys Ic Validator
• Cadence Virtuoso
• Vlsi
• Physical Design
• Verilog
• Stcl
• Synopsys Starrc
• Unix
• Perl
• Eda
• C
• Analog
• Cadence Assura