Sukrutha Rajashekar Murthy

Digital ASIC RTL Design Engineer | SystemVerilog • CDC/RDC • SpyGlass • Synopsys DC | 90%+ First-Pass Synthesis | SoC Front-End Specialist

Role
Digital Asic Front-end (Rtl) Design Engineer at HCLTech
Location
Syracuse, NY, US
LinkedIn followers
500 followers

About Sukrutha Rajashekar Murthy

I\'m a Digital ASIC Front-End Engineer who turns complex micro-architecture specs into clean, synthesizable RTL — the kind that handoff teams actually thank you for. With SystemVerilog, Verilog, and VHDL as my core toolkit, I specialize in building high-performance digital blocks that work right the first time, across multi-clock SoC environments.

Experience

  1. Digital Asic Front-end (Rtl) Design Engineer

    HCLTech

    Dec 2025 — Present · US

    Led RTL design and detailed micro-architecture implementation for high-performance digital ASIC blocks using System Verilog, delivering 100% synthesizable, timing-clean RTL across complex multi-clock SoC environments. Designed reusable and parameterized RTL modules in System Verilog and Verilog, achieving ~20% reduction in logic utilization while enabling efficient scalability across multiple silicon configurations Executed comprehensive CDC and RDC analysis using Spyglass, identifying and resolving 95%+ critical clock and reset crossing issues during early front-end stages to prevent late-cycle design risks. Developed and validated SDC timing constraints for advanced clocking architectures, improving front-end STA readiness by ~30% and ensuring smooth handoff to physical design teams. Performed RTL linting, peer code reviews, and design audits, improving overall code quality metrics by 35% and ensuring compliance with internal ASIC coding and low-power standards. Supported RTL simulation, debug, and assertion-based validation, reducing functional defect resolution time by ~25% through efficient waveform analysis and structured root-cause investigation. Worked within Agile SDLC frameworks, consistently meeting 100% sprint and milestone commitments while collaborating closely with verification and integration teams during design reviews.

Education

  • Syracuse University College of Engineering and Computer Science

    Master of Science - MS, Electrical Engineering

  • Visvesvaraya Technological University

    Bachelor of Engineering - BE, Electrical, Electronics and Communications Engineering

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Sukrutha Rajashekar Murthy — Digital Asic Front-end (Rtl) Design Engineer at HCLTech in Syracuse, NY, US | Unifers