Sukant Dewangan
- Role
- Design Verification Lead at Google
- Location
- Bengaluru, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Sukant Dewangan
12 years of IP/Subsystem Design Verification experience in VLSI industry. I have worked…
Experience
Design Verification Lead
Aug 2023 — Present
Memory Controller IP DV
Skills
- Verilog
- Uvm
- Data Structures
- Fpga
- C++
- Cadence Virtuoso
- Microcontrollers
- Modelsim
- Algorithms
- Microprocessors
- C/C++ Stl
- Linux
- Programming
- Integrated Circuit Design
- Perl
- Asic
- C
- Debugging
- Arm Architecture
- Field-Programmable Gate Arrays (Fpga)
- Pspice
- Soc
- Universal Verification Methodology (Uvm)
- Php
- Vhdl
- Vlsi
- System on a Chip (Soc)
- Embedded Systems
- Computer Architecture
- Spice
- Arm
- Rtl Design
- Systemverilog
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