Sujith P.

About Sujith P.

10+ years of full-time experience in ASIC and FPGA design.1+ year of experience in academic research and as a student intern in ASIC, and FPGA-based design, RTL coding, low power design, design verification, linting, synthesis, CDC, LEC, Code coverage and lab debugging (FPGA Validation).Programming skills: System Verilog, Verilog, VHDL, C, C++, Python, PerlDevelopment tools: Vivado, Xilinx ISE, Synopsys Design Compiler, Novas Verdi, Conformal, Spyglass, Power Artist, Modelsim, Questa CDC, Quartus II, Cadence Design Suite (spectre), Cadence Virtuoso, Encounter, Matlab, Simulink, Ltspice Platforms: Windows, Linux, Unix

Experience

1. Principal Mts - Asic Fpga

   Lyte

   Aug 2023 — Present · Mountain View, CA, US

   Building foundation for Physical AI

Education

• University of Florida

  MS, Electrical and Computer Engineering

  2011 — 2013

Skills

• Cadence Virtuoso
• Vlsi
• Logic Design
• C++
• Simulink
• Simulation
• Ltspice
• Verilog
• Pspice
• Computer Architecture
• Rtl Coding
• Spectre
• Rtl Design
• Synopsys Tools
• Matlab
• Conformal Lec
• Hardware Design
• Perl
• Fpga
• Asic
• C
• Cdc
• Modelsim
• Digital Design
• Xilinx
• Vhdl
• Lint