Sujith M. B.
Senior Analog Layout Designer
- Role
- Senior Design Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Senior Design Engineer
Aug 2022 — Present · Bengaluru, IN
Education
University of Calicut
Bachelor of Technology (B.Tech.), Electrical, Electronics and Communications Engineering
2007 — 2011
Karunya Institute of Technology and Sciences
Master's degree, VLSI Design
2012 — 2014
Sree Valluvanad Vidhya Bhavan
Schooling, Science
1993 — 2007
Skills
- Synopsys Tools
- Microsoft Office
- Cadence Virtuoso
- Programming
- Windows
- Verilog
- Semiconductors
- Electronics
- Vhdl
- Simulations
- Cadence Spectre
- Very-Large-Scale Integration (Vlsi)
- Tcad
- Java
- Matlab
- Linux
- Physical Verification
- Calibre
- Layout Design
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