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Sujith Hiremath

Hiring Principal Engineers, Design Verification

Role
Senior Principal Engineer at Cadence
Location
Bengaluru, KA, IN
LinkedIn followers
500 followers
EngineeringView LinkedIn profile

About Sujith Hiremath

Expertise in verification of SOCs, Memory Subsystems, SERDES and Hardware Security IPs, having worked on designs for Crypto, Encrypted memory sub-system, PCIe Gen3, SATA 3, USB 3/3.1, DDR3/4, LPDDR3 and HBM among other protocols.

Experience

  1. Senior Principal Engineer

    Cadence

    Dec 2021 — Present · Bengaluru, IN

Education

  • PES Institute of Technology

    B.E., Electronics and Communication

    2006 — 2010

Skills

  • C/C++
  • Systemverilog
  • Perl
  • Test Bench Bring-Up
  • System Verilog Assertions
  • Uvm
  • Open Verification Methodology
  • Verilog

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Sujith Hiremath — Senior Principal Engineer at Cadence in Bengaluru, KA, IN | Unifers