Sujit Singh
Staff Analog Layout Engineer at Marvell Technology
- Role
- Staff Analog Layout Engineer at Marvell Technology
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Sujit Singh
Technology :sec4lpe, tsmc n4, sec5lpe, 7nm,10nm,16nm, 22nm, 45nm. Tools : Cadence Virtuoso, Genesys Layout Editor : layout XL, EXLFoundry Exposure: TSMC, Samsung, Intel, Global Foundry, Layout Verification : Calibre and Assura.SKILL coding.Good knowledge of Analog and Digital Signal Layout Design.Experienced in hierarchical design implementation of floorplan, multiple block integration, signal and power routing at Chip level.Worked on Different analog Blocks like Receiver, Equalizer, rxdatalane, Pi_top, PM_TOP, ADC, PLL, BGR, LDO, CLK Buffers, Global_commontop in SERDES project, LFRX, Rxdatatop, TX top, Clk top, Level Shifter in MiPi Dsi project. Experienced in Physical Verification Checks - DRC, LVS, ERC, IR-drop, EM, S-factor, Antenna, Float checks at Chip level.
Experience
Staff Analog Layout Engineer
Jun 2022 — Present · IN
Education
Sree Ayyappa Public School
High School
2010 — 2012
College of Engineering (CEB), Bhubaneswar
Bachelor of Technology - BTech
2012 — 2016
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