Suhas N
Driving Robust LP & Formal Equivalence Verification (FEV/LEC) CAD Flows for Complex SoCs
- Role
- Staff Engineer, Applications Engineering at Synopsys Inc
- Location
- Hillsboro, OR, US
- LinkedIn followers
- 500 followers
About Suhas N
Staff Product Engineer @ Synopsys Inc, with main focus on Logical Equivalence Checking and Low Power Design Verification. Experienced in debugging Logical Non-Equivalences in designs with the help of Equivalence Checking tools and Static Checkers. Proficient in debugging logical failures in multiple customer CAD flows.My specialties include: Synthesis (Logic, Hierarchical and Low Power), LEC, Formality-LP, CLP/VC-LP, Automated ECO.
Experience
Staff Engineer, Applications Engineering
Aug 2022 — Present · Hillsboro, OR, US
Product Feature Testing & Creating Test Plans for Formality UPF related features Experienced in identifying and resolving FM All PST failures due to PDCuts, Isolation, Unknowns, FPM etc, Fusion Compiler and Design Compiler Front End Bad Logic / Bad Datapath debug Handled SVF(.vsdc) guidance related issues contributing to failures and hard verification Proficient in setting up and debugging FM_LP two design + two UPF checks Helping clients to setup low power LEC and ECO flows using their scripting environments Experienced in generating Interactive / Manual ECOs using Formality Ultra Actively involved in training Formality Copliot AI knowledge assistant tool Created TCL / Python scripts to automate VC LP / FM LP setup, result analysis, and report generation, reducing manual effort.
Education
Visvesvaraya Technological University
Bachelor of Engineering in ECE, Electronics and Communication
2009 — 2013
PES University
Master of Technology (M.Tech.), VLSI design and embedded systems
2014 — 2016
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