Suhas H R

About Suhas H R

Design Verification Engineer driving SoC RTL verification and Gate-Level Simulation (GLS) for ARM-based pre-silicon ASIC programs.Core Expertise:• SoC-level RTL functional verification, full-chip regressions, and cross-IP debug using SystemVerilog and C/C++ tests• Coverage closure (Branch / Toggle / Expression) and targeted testcase development for milestone signoff• SystemVerilog Assertions (SVA) and Q-Formal connectivity validation prior to GLS• GLS environment bring-up, zero-delay and SDF-annotated simulations across timing corners• Power-Aware GLS validation (UPF intent, isolation logic, retention behavior, power sequencing)• Debug of X-propagation, timing violations, boot failures, and clock-related issues• GLS vector generation and ATE pattern conversion to support silicon bring-up and pre/post-silicon correlation

Experience

1. Design Verification Engineer

   Capgemini Engineering

   Mar 2022 — Present · Bengaluru, IN

   Client : Qualcomm • Executed zero-delay and SDF-annotated Gate-Level Simulations (GLS) across timing corners to ensure pre-silicon signoff readiness• Debugged X-propagation, boot failures, and clock-related issues at gate-level in collaboration with DV and design teams• Converted post-DV simulation outputs into ATE vector formats (.BIN.hptab) to support silicon bring-up and production testing• Performed Power-Aware GLS validation (isolation logic, power sequencing, UPF intent) across multiple SoC/IP blocks)Client : Microchip Technology • Drove SoC-level RTL functional verification across multiple IPs, executing full-chip regressions and resolving complex functional mismatches• Led GLS environment bring-up, executing zero-delay and SDF-annotated simulations across timing corners• Identified and resolved X-propagation and timing-induced gate-level failures prior to milestone signoff• Performed formal verification (Q-Formal) for analog IP connectivity validation before GLS signoff• Achieved coverage closure (Branch/Toggle /Expression/FSM) through gap analysis and targeted testcase development• Collaborated with RTL, physical design, and validation teams to stabilize pre-silicon simulations before tape-out

Education

• Visvesvaraya Technological University

  Bachelor's of Engineering - BE, Electronics and Communications Engineering

• Alva's College, Moodabidri, Karnataka

  Pre-university