Sugun Kedambadi
Design Verification Engineer | UVM, FPGA
- Role
- Verification Engineer at Microsoft
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
Information TechnologyView LinkedIn profile
About Sugun Kedambadi
My professional journey is rooted in a desire to drive excellence in hardware development through meticulous verification processes and a continuous learning approach.
Experience
Verification Engineer
Jul 2025 — Present
Azure cloud acceleration
Education
University of California, Davis
MS, Electrical Engineering
1997 — 1999
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