Sudhir Shetty
Group Director of Design Engineering - Memory Interface IP Group ||||||| Hiring 2 to 20+ exp|| Digital Design | Firmware || DDR | LPDDR | HBM | GDDR Memory Subsystem | IP Design
- Role
- Design Engineering Group Director at Cadence
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Sudhir Shetty
Hands-on Engineering leader and RTL IP design Engineer with 20+years of experience in…
Experience
Design Engineering Group Director
Jul 2024 — Present · Bengaluru, IN
Education
Visvesvaraya Technological University
Master of Technology - MTech
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