Sudheesh V R
Intern @Seidor Opentrends India
Palakkad, KL, IN
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WORK HISTORY
Oct 2024 — Present
Intern @Seidor Opentrends India
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Developed a automated the digital ASIC design process from Verilog code generation to GDSII layout, powered by Generative AI and open-source EDA tools.
EDUCATION
N/A
Kerala University of Digital Science, Innovation and Technology
Master's degree, Electronics
2018 — 2021
University of Calicut
Bachelor's degree, electronics
ABOUT SUDHEESH V R
Post Graduate student- Electronics VLSI, Digital University Kerala
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