Sudheer Vemula

About Sudheer Vemula

PROFILE SUMMARY 15 years experience as SOC/ASIC Front end Verification Engineer• Good knowledge on protocols –AHB, APB, USB2, I2C, SMBUS, SPI, UART, Fiber Channel Protocol,• Hands on experience on cadence VIPs(PureView) and tools. • Extensive Verification experience including definition and development of Verification Environment, test case and test plan definition and development, functional coverage and Regression.• Experience in SystemVerilog (OVM/UVM) Constrained Driven Verification Environment and VIP development• Experience in developing Reference model in C++. Worked on perl scripting.• Development of checkers/assertions using PSL Assertion and SVA.Specialties: c, c ++, cryptography, doors, ethernet, perl, pvcs, perl scripting, verilog, vhdl, system verilog, OVM, UVM,AVM, cadence, simvision, mentor graphics,vcs,fiber channel protocal

Experience

1. Design Verification Engineer

   Meta

   Jan 2026 — Present · Sunnyvale, CA, US

Education

• Vellore Institute of Technology

  B.Tech, Electronics and Instrumentation

  2003 — 2007

Skills

• Logic Synthesis
• Field-Programmable Gate Arrays (Fpga)
• Uvm
• Ethernet
• Semiconductors
• Integrated Circuit Design
• Arm
• I2c
• Rtl Design
• Very-Large-Scale Integration (Vlsi)
• Rtl Coding
• C
• Verilog
• Ncsim
• Functional Verification
• Spi
• Amba Ahb
• Application-Specific Integrated Circuits (Asic)
• Hardware Architecture
• Open Verification Methodology
• Usb
• Fpga
• Perl
• Embedded Systems
• Eda
• Asic
• Uart
• Integrated Circuits (Ic)
• Modelsim
• Soc
• Static Timing Analysis
• Vlsi
• Service Provider Interface (Spi)
• Cadence
• Ic
• Tcl
• Vhdl
• System on a Chip (Soc)
• Digital Signal Processors
• Systemverilog