Sudhansh Garg
FPGA IP Logic Design @ Intel Corporation ✅
- Role
- Fpga Ip Logic Design Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Sudhansh Garg
A Design Engineer who always is in search of improving knowledge and skills. FPGA Design and Validation Engineer (FPGA, RTL Development, Board Validation on Xilinx RFSoC, Intel Arria 10, Stratix10 and Agilex), Verilog, VHDL. Experience in Multi Gig Ethernet, DDR4 and various wireless domain applications. Integration of IP\'s with multiple clock domain using various tools (Vivado/Quartus). Debug using ILA/Chipscope/Signal Tap analyzer. Also worked along with RF team for validation of DDC/DUC, IQ correction and DC imbalance correction blocks. Basic knowledge in handling Signal generators and Spectrum analyzer.Experience in Python, MATLAB, BASH scripting. Rich experience in working on Linux platform.
Experience
Fpga Ip Logic Design Engineer
May 2022 — Present · Bengaluru, IN
Handling Multi-gig Ethernet IP’s for new feature implementation on Agilex devices. Also involved in handling critical bugs raised by customers.
Education
Sandeepani School of VLSI Design
Professional Diploma, FPGA/ASIC Design and Verification
SRM IST Chennai
Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering
2013 — 2017
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