Sudershan Reddy Yanumala Venkata
Analog Design Verification Engineer at Texas Instruments
- Role
- Analog Design Verification Engineer at Texas Instruments
- Location
- Tempe, AZ, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Analog Design Verification Engineer
Jan 2026 — Present · Phoenix, AZ, US
Education
Texas A&M University
Master of Science - MS, Electrical and Electronics Engineering
BV Raju Institute of Technology (BVRIT)
Bachelor of Technology - BTech, Electronics and Communication Engineering
Sri Chaitanya Junior College, Bhaskar Bhavan
Intermediate, MPC
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