Sudeep Mourya
Post Silicon Validation Intern @INTEL | Python Scripting | Automation | Validation | Testing || Design Verification Trainee @VLSI Guru | Verilog | SystemVerilog | UVM | AMBA || MTech - VLSI Design - VIT University |
- Role
- Design Verification Engineer Trainee at Vlsiguru Training Institute
- Location
- Indore, MP, IN
- LinkedIn followers
- 500 followers
About Sudeep Mourya
Design Verification Engineer Trainee with technical knowledge. Hands-on experience in…
Experience
Design Verification Engineer Trainee
Jun 2024 — Present · Bengaluru, IN
Education
Kendriya vidyalaya
SSC
2013 — 2014
Kendriya vidyalaya
HSC
2015 — 2016
Vellore Institute of Technology (VIT)
Master of Technology - MTech
2022 — 2024
Ujjain Engineering College, Sanwer Road, Ujjain
Bachelor of Engineering - BE
2016 — 2020
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