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Sudarshan Vempati

Role
Design Verification Engineer at Meta
Location
San Jose, CA, US
LinkedIn followers
500 followers
EngineeringView LinkedIn profile

About Sudarshan Vempati

ASIC Verification engineer with expertise in Testbench environment development using…

Experience

  1. Design Verification Engineer

    Meta

    Oct 2022 — Present

Skills

  • Testing
  • C++
  • Perl Script
  • Very-Large-Scale Integration (Vlsi)
  • Embedded Systems
  • Unix Shell Scripting
  • Computer Architecture
  • Systemverilog
  • Field-Programmable Gate Arrays (Fpga)
  • Vlsi
  • Firmware
  • Embedded Software
  • Shell Scripting
  • Application-Specific Integrated Circuits (Asic)
  • Device Drivers
  • Vhdl
  • Simulations
  • C
  • Verilog
  • Debugging
  • Integrated Circuits (Ic)

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Sudarshan Vempati — Design Verification Engineer at Meta in San Jose, CA, US | Unifers