Sudarshan H N

About Sudarshan H N

Technical leader driving next generation Data Center CPUs working across product, architecture/RTL, physical design and post silicon teams to improve PPA and build best in class designs in speed of light timeframe.

Experience

1. Director of Hardware Engineering

   NVIDIA

   Jan 2012 — Present · San Francisco, CA, US

   Drove physical design for the Vera CPU Complex, delivering NVIDIA’s first multi-threaded custom CPU with second-generation System Coherency Fabric (SCF). Led tight cross-functional co-design with Architecture and RTL, and partnered closely with Product and Silicon Bring-Up teams to accelerate frequency, performance, and time-to-tapeout improvements. • Physical Design Lead for Grace CPU, architecting and owning the entire PD lifecycle — from POR definition, frequency and power trade-offs, and floorplanning to full physical implementation and timing closure. • Led Physical Design for System Coherency Fabric on NVIDIA Xavier SoC, owning floorplanning, synthesis, multi-voltage timing strategy, and timing closure for a complex, high-performance fabric.

Education

• University of California, Berkeley

  Certificate Program in Leadership and Management, Organizational Leadership

  2016 — 2017

• R V College of Engineering

  B.E

  2001 — 2005

• Birla Institute of Technology and Science, Pilani

  M S, Microelectronics

  2008 — 2010

Skills

• Timing Closure
• Very-Large-Scale Integration (Vlsi)
• Logic Synthesis
• Microprocessors
• System on a Chip (Soc)
• Integrated Circuits (Ic)
• Ic
• Formal Verification
• Vlsi
• Usb
• Ddr
• Physical Design
• Soc
• Asic
• Primetime
• Static Timing Analysis
• Timing
• Verilog
• Silicon
• Application-Specific Integrated Circuits (Asic)