Suchismita Padhy
Analog IC Layout Engineer | Advanced Node Expertise (Intel 5nm, TSMC 3nm) | Cadence Virtuoso, DRC/LVS, EM/IR | Seeking Next Challenge
- Role
- Associate I-associate E E & Semiconductor Engineer at Capgemini Engineering
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Suchismita Padhy
I am an Analog & Mixed-Signal Layout Engineer with hands-on experience in advanced…
Experience
Associate I-associate E E & Semiconductor Engineer
Sep 2022 — Present · Bengaluru, IN
Independently design and implement analog and digital layouts from scratch using Cadence Virtuoso (EXL) and verification tools like Assura for process nodes ranging from 180nm, GPDK 90/45nm, Intel 5nm to TSMC 3nm.Responsibilities Design and develop digital standard cells (AND, OR, NOT, NAND, NOR, XOR, XNOR, MUX, DFF) from scratch, ensuring DRC and LVS clean layouts using Cadence Virtuoso (MXL) and Assura across 180nm to TSMC 3nm nodes Create complex analog and mixed-signal layouts including amplifiers, bandgap references (BGR), current mirrors, differential pairs, and multistage op-amps Execute floorplanning, placement, routing, and timing analysis to optimize area, power, and performance Apply advanced device matching techniques such as common centroid and interdigitated matching to reduce mismatch and improve analog precision Perform parasitic extraction, metal density checks, shielding (parallel and coaxial), and power mesh generation to ensure signal integrity Conduct thorough verification including DRC, LVS, EM/IR analysis, antenna effect mitigation, ESD protection, latch-up prevention, and well proximity effect analysis Collaborate closely with schematic designers, verification teams, and process engineers for design optimization and manufacturabilityKey Achievements Successfully delivered multiple DRC/LVS clean digital standard cells crucial for SoC integration across various nodes Led analog layout design for high-performance blocks like amplifiers and BGR circuits with stringent matching and noise immunity requirements Implemented advanced shielding and power integrity techniques improving layout reliability and reducing design re-spins Developed efficient layout flows and best practices that boosted team productivity and sped up turnaround times Contributed to projects on Intel 5nm and TSMC 3nm nodes, gaining hands-on experience with industry-leading process technologies
Education
Parala Maharaja Engineering College, Berhampur
Bachelor of Technology - BTech, Electronic and Communications Engineering Technology/Technician
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