Subrat Vicky
Timing at Apple
- Role
- Timing at Apple
- Location
- Austin, TX, US
- LinkedIn followers
- 500 followers
OperationsView LinkedIn profile
About Subrat Vicky
Static Timing Analysis(STA), Full Chip Timing closure for Graphics Core/ARM Core, Pre…
Experience
Timing
Dec 2019 — Present · Austin, TX, US
Timing closure for some cool products
Education
Birla Institute of Technology and Science, Pilani
B.E.(Hons.)
2004 — 2008
Skills
- Debugging
- Floorplanning
- Low-Power Design
- Static Timing Analysis
- Vlsi
- Physical Design
- Perl
- Clock Tree Synthesis
- Power Analysis
- Soc
- Semiconductors
- Asic
- Integrated Circuit Design
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