Subrahmanyam Gantasala
Senior DV Engineer @ Qualcomm | Lam Research | IITM
- Role
- Senior Design Verification Engineer at Qualcomm
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Subrahmanyam Gantasala
I’m a Design Verification Engineer with 3.5 years of experience in ASIC and FPGA systems. I enjoy understanding how processors, memories and on-chip fabrics work and building test environments that make them more reliable.At Qualcomm I work on low-power AI subsystems where I verify RISC-V paths, memory features and system power behaviour. Earlier at Lam Research I worked on FPGA design and verification, RTL migration and UVM-based testbenches.I like solving tricky debug problems and writing simple, clear verification infrastructure. Outside work I explore DV side projects, travel and watch movies.Happy to connect with people working in DV, subsystems or FPGA or ASIC design.
Experience
Senior Design Verification Engineer
Jul 2024 — Present · Bengaluru, IN
Education
Indian Institute of Technology, Madras
Master of Science - MS
2020
2021 Qiskit Global Summer School on Quantum Machine Learning
Certificate of Quantum Excellence, Quantum Computing, Quantum Machine Learning
Jawaharlal Nehru Technological University, Kakinada
Bachelor of Technology, Electronics and Communications Engineering
2016 — 2020
Frontier Technology Institute
Quantum Computing
2020 — 2021
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