Subhash Iyer
Sr. Program Manager & Chief of Staff at AMD
- Role
- Sr Manager Program Managment & Chief of Staff at AMD
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Subhash Iyer
Profile Summary: Proven leader in multiple roles with a strong intrapreneurial drive…
Experience
Sr Manager Program Managment & Chief of Staff
Jul 2024 — Present · Bengaluru, IN
Sr Manager - Program Management and Chief of Staff for the S3 (Strategic Silicon Solutions) SOC team, responsible for ensuring that new product development program execution is successfully driven in line with the project(s) scope, schedule, and budget. A key component of this role involves working closely with internal and third-party IP suppliers, an SOC team spread across the globe and the SOC architecture team to ensure continual forward progress is maintained, status reporting is timely and accurate and key issues are driven with appropriate urgency. This is a cross-functional role that involves engagement across all engineering disciplines and business units to meet project objectives. KEY RESPONSIBILITIES:Delivering on all assigned program commitments from inception through execution to tapeout & productionResolving cross-domain dependencies and enabling progress to meet planned scheduleDelivering assigned program(s) within schedule, budget and scopeDriving program scoping & development cost roll up for a given budget, customer requirements & SOC bounding box.Acting as a key liaison between IP and SOC execution teams on all matters pertaining to successful project execution, IP delivery and negotiationDriving incorporation of initiatives and process improvements at the functional, cross-functional, and corporate level into assigned program(s)Ownership of status reporting and issue messaging to key stakeholders, including senior executives and customers
Education
Nagpur University (RKN Engineering College)
BE, Electronics Engineering
1995 — 1999
C-DAC ATC (Soft Polynomials)
Post Graduate Diploma in VLSI Design, VLSI Design - VHDL, Digital Circuits, FPGA, Coding, Simulation and Analysis
1999 — 2000
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