Subhash Sangam

About Subhash Sangam

10+ years of experience in functional verification of RTL.• Experienced in defining the Verification strategies and planning test bench architecture, and writingtestplans for system-level testing of designs to achieve test objectives.• Experienced in verification of internal Memory Sub systems and Memory controller in Modem chip sets.• Experienced in writing scripts to speed up the UVM test bench creation in Perl and Perl-Tk• Ran Gate level simulations and helped the Physical Design team with timing closure and power analysis.• Created CPF files and ran CLP (Conformal Low Power ) on mixed signal design.• Created many UVM standalone test benches from scratch.• Drove the debug efforts along with the RTL, Architecture, Circuit design, Consumers teams and derivedoptimal solutions for the problems found.• Experienced writing constraint randomization items for coverage closure and also experienced in creatingFunctional coverage models.• Led a team of 4 while working on a project, updating the daily status and generating regression reports.

Experience

1. Staff Design Verification Engineer

   Samsung Semiconductor

   Jun 2015 — Present · San Francisco, CA, US

   Developed a standalone UVM testbench from scratch to verify proprietary serial interface bridge. • Wrote multiple UVM agents (APB Master/ APB Slave/ SPI Slave) from scratch and developed a scoreboard to support serial to APB and serial to SPI bridge verification.• Developed a UVM test bench to verify the Zigbee MAC protocol. Actively involved and supported the top level integration team in porting test cases from block level to top level.• Used Constrained randomization to create different types of MAC frame type and used them to close the functional coverage.• Worked on Baseband RxFilter verification based on vector flow.• Developed a GUI using Perl-tk which would develop the skeleton for UVM testbench architecture and needed agents.• Ported standalone Serial interface sequences to the top level and helped with verification closure.

Education

• San José State University

  M.S, Electrical Engineering

  2006 — 2008