Subhash Joshi

About Subhash Joshi

Leading ASIC DV teams developing next generation AI SoCs @ Google Silicon.• Lead USB4/TBT AV/DV team. IP/SS/FPGA Client & Discrete SoCs.• Diversified work experience on different aspects of VLSI-ASIC/FPGA RTL design and Design verification (IP designing and SoC/Subsystem/IP verification).• Lead DV Effort on Functional, Power & Performance vertical for multiple Architecture.• Played a pivotal role in delivering industries one of the earliest LPDDR solutions, Thunderbolt and UFS technology• Verification signoff for Multiple IP/SS/SoCs.• Hands-on Experience with RTL Design and FPGA prototyping for High speed serial protocol• TB/Verification Environment development from scratch and Verification closure.• Verification/TB infrastructure development using SV and reusable TB-framework development for verification of other sub-modules in IP.• Have an exposure on various on-chip bus protocol architectures like AXI, SPACE-FIBER/ PCI-Ex, and USB. Off-chip buses like I2C and SPI, Other protocols like Ethernet and WiMAX.• Ex-Intel, Ex-Qualcomm prior to QC worked with NEC Research Lab, Japan & Creative Solutions.

Experience

1. Asic Dv Manager Google

   Google

   Feb 2023 — Present

Education

• CDAC-Pune

  VLSI

• Birla Institute of Technology and Science, Pilani

  Master’s Degree, Microelectronics

Skills

• Perl
• Embedded Systems
• Eda
• Soc
• Vlsi
• Functional Verification
• Systemverilog
• C++
• Static Timing Analysis
• Fpga
• Asic
• Very-Large-Scale Integration (Vlsi)
• Rtl Design
• C
• Application-Specific Integrated Circuits (Asic)
• Verilog
• Field-Programmable Gate Arrays (Fpga)
• System on a Chip (Soc)