Steven Carlough

About Steven Carlough

Microprocessor design lead: Expert in the design of Enterprise Class microprocessors with clock rates exceeding 5 GHz. Experienced leading teams in the design of high availability error tolerant fixed & floating point execution units. Chip lead for Server Class ASICs: Experience designing and leading the development of Server class ASICs including a DDR4 Smart memory controller used to interface an OMI 32 GBps high speed serial link to DDR4 memory. Experience evaluating 3rd party vendor IP capabilities such as DDR and HSS PHYs. IBM Master Inventor, appointed based on development of Intellectual Property. Extensive experience leading geographically diverse and inclusive development teams. Innovation that matters: 92 Patents granted.

Experience

1. Microprocessor Design at Amd

   AMD

   Sep 2022 — Present · New York, NY, US

Education

• Rensselaer Polytechnic Institute

  PhD Electrical Engineering, Thesis: Processor Design Using Heterojunction Bipolar Transistor Technology

  1989 — 2000

Skills

• Analog Circuit Design
• Logic Design
• Debugging
• Computer Hardware
• Fpga
• High Performance Computing
• Microprocessor Design
• Hardware Architecture
• Processors
• Cmos
• Microprocessors
• Vhdl
• Verilog
• Ic
• Vlsi
• Circuit Design
• Perl
• Computer Architecture
• Computer Arithmetic
• Hardware