Steve Holloway
Senior Member of Technical Staff @Renesas Electronics
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WORK HISTORY
Senior Member of Technical Staff @Renesas Electronics
Development and support of Common Verification Platform which provides a single verification environment capable of running Formal/Digital/Digital-Mixed-Signal/Analog-Mixed-Signal verification tasks. Key contributor to Accellera UVM-Mixed Signal standard. Consultant role on multiple Power Management IC projects. Verified several subsystems and contributed improvements to Renesas UVM methodology. Developed automated Formal Verification flow based on template generators and internal FV apps.
ABOUT STEVE HOLLOWAY
25 years experience in verification primarily for consumer electronics ASIC projects in groups with an excellent record of achieving high functionality first silicon. Verification lead on a number of complex SoC designs with large numbers of IP and aggressive timescales. Track record of technical team leadership, developing planning & monitoring progress. Driving forward functional improvements, delivering knowledge sharing events, coaching team members. Key contributor to the Accellera UVM-Mixed Signal extension.Specialties: UVM, SystemVerilog, Formal Verification, VHDL, Verilog, C++, SystemC, Specman ‘e’, python, perl, tcl, shell scripting, Makefile
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