Steve Cheng
principal engineer
- Role
- Principal Design Engineer at Etopus Technology
- Location
- Santa Clara, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Steve Cheng
112G Serdes system in 7nm process with 56G 7bit SAR ADC 56G Serdes system in 16nm…
Experience
Principal Design Engineer
Jul 2016 — Present
Skills
- Integrated Circuit Design
- Fpga
- Asic
- Pll
- Cadence Spectre
- Eda
- Cadence Virtuoso
- Serdes
- Cadence
- Ic
- Debugging
- Verilog
- Simulations
- Mixed Signal
- Circuit Design
- Semiconductors
- Verilog-a
- Matlab
- Analog Circuit Design
- Soc
- Analog
- Cmos
- Spectre
- Rf
- Hardware Architecture
- Hdmi
- Vlsi
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