Stephen Ramey
Principal Engineer and Manager of the Transistor Reliability Modeling Group at Intel
- Role
- Engineering Manager at Intel
- Location
- North Plains, OR, US
- LinkedIn followers
- 500 followers
About Stephen Ramey
Internationally recognized transistor reliability expert with over 60 publications in the…
Experience
Engineering Manager
Oct 2003 — Present · Hillsboro, OR, US
I manage the transistor reliability group responsible for developing all of the logic CPU process technologies in research and development. Prior to this role, I owned transistor reliability aspects of Intel\'s various leading edge process technologies, including a seven year project guiding the development of the revolutionary 22nm tri-gate technology from concept through R&D to commercialization. My main areas of expertise involve modeling and optimizing process development for gate oxide breakdown and transistor aging (BTI and hot carrier degradation).
Education
Carnegie Mellon University
B.S., Physics
Arizona State University
Ph.D., Electrical Engineering
2000 — 2003
University of Nevada-Las Vegas
MS, Electrical Engineering
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.