Stephane Cattaneo
Soc - Rf System Validation and Fpga & Prototyping Manager @STMicroelectronics
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WORK HISTORY
Soc - Rf System Validation and Fpga & Prototyping Manager @STMicroelectronics
Grenoble, FR
In charge of mapping SOC on presilicon platform (Palladium/FPGA) and performing digital, and RF system validation.
EDUCATION
Université Joseph Fourier (Grenoble I)
DUT Mesures Physiques
Grenoble INP - UGA
ENSERG option semiconductors, Semiconductor
SKILLS
ABOUT STEPHANE CATTANEO
Experienced Validation Manager with a demonstrated history of working in the semiconductors industry. Skilled in Embedded Software, Device Drivers, Embedded Linux, Semiconductor Industry, and Silicon. Strong quality assurance professional with a ENSERG option semiconductors focused in Semiconductor from Institut national polytechnique de Grenoble.
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