Stéphane Gros
Engineering Manager Silicon Verification @Axelera AI
Nice, FR
EMAILS
MOBILE NUMBERS
+91 *********19
Signup · Get unlimited contacts
WORK HISTORY
Jul 2025 — Present
Engineering Manager Silicon Verification @Axelera AI
View department →
Antibes, FR
EDUCATION
2007 — 2009
Université Joseph Fourier (Grenoble I)
Two-years degree specialized in Electronics engineering (DUT GEII)
2011 — 2012
KTH Royal Institute of Technology
Exchange semester
2009 — 2012
Grenoble INP - UGA
Master's degree in engineering
SKILLS
Rtl DesignSystemcWordDebuggingCssSystemverilogDesign VisionEmbedded SoftwareAsicSocPrecisionVerilogPspiceHtmlVisual Basic .netCAgilent AdsIntegrated Circuit DesignAltium DesignerUnixC++JavascriptVisual StudioHardware ArchitectureLatexPslCadenceJavaUniversal Verification Methodology (Uvm)PowerpointExcelAssemblyVhdlModelsimVimPerlEmbedded Systems
ABOUT STÉPHANE GROS
Engineering Manager – Silicon Verification at Axelera AI
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.