Steen Larsen

About Steen Larsen

20+ years in the technology industry developing value in future product architectures (platform, SoC, and IP). By learning and iterating on end customer usage models, the needs for cost, power, performance architectural tradeoffs can be determined and documented in specifications clearly. With design and validation team input I help build consensus and alignment to drive the best possible product in a timely delivery. My background has ranged from direct OEM architecture discussions (HPE, Dell, Lenovo,Apple) to RTL gate level decisions on power managment, RAS, error, debug, and performance logging to help define the best possible solution under the constaint requirements.While much of my background is more hardware and architecture oriented, SW is a continuous and important thread. My year in in virtual OS kernel performance exposed me to many important aspects of memory type tiering and benchmark metrics.While I have had the honor of working with smart people on several patents and papers, the ones I am most proud of are:USPTO 82•••48 Leveraging DRAM memory controller “critical chunk” latency control idea to implement a NIC frame “critical byte” control to reduce network latency, showing the benefit of a broad background.USPTO 80•••12 Using the NIC traffic density to modulate core power states to process traffic and optimizing system power efficiency, showing the importance of carefully balancing engineering tradeoffs to get the best result.

Experience

1. Sr Staff System Architect

   Penguin Solutions

   Feb 2025 — Present

   Defining memory architecture on optical and CXL interfaces.

Education

• Oregon State University

  MS, Electrical and Electronics Engineering

  1993 — 1997

• Oregon State University

  Bachelor of Science - BS

  1988 — 1991

• Oregon Health & Science University

  MST, Management in Science and Technology

  2001 — 2004

• Oregon State University

  PhD, Computer Engineering

  2010 — 2015