Saikrishna Siripuram
Lead Design Engineer,AMS Layout @ Cadence Design Systems
- Role
- Lead Design Engineer at Cadence
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Saikrishna Siripuram
Expertise in Rx,Tx,Macro level ESD and PLL(RO,LC).Familiar nodes:TSMC3,TSMC5,TSMC7,TSMC28SAMSUNG 4, SAMSUNG 5GF12,GF14,GF22FDSOIIntel18A,Intel18AP,Intel3Protocols worked on:USB2/3/4,PCIE2/3/4,VSR(128G),XSR(128G),eUSB,MIPI,Multipritocol SERDES.Familiar with Synopsys Custom Compiler and Cadence virtuoso.Familiar with Cadence release flow(CHECK IT) and Synopsys release flow(HIPRE).Expertise in defining methodology for new tech nodes.
Experience
Lead Design Engineer
Sep 2024 — Present · Hyderabad, IN
Education
JNTUH College of Engineering Jagityala
Bachelor of Technology - BTech, Electrical and Electronics Engineering
2015 — 2019
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