Srujana Mojerla

About Srujana Mojerla

SoC Design Verification Engineer with 3 years of experience specializing in Pre-Silicon Performance Validation for Intel Server SoCs.* Expertise in RTL design and debugging, performance analysis, and optimization.* Proficient in SystemVerilog, UVM, Python, C, Data Structures and industry-standard tools.* Passionate about Digital VLSI Design and High-Performance Computer Architecture.

Experience

1. Soc Design Engineer

   Intel

   Aug 2021 — Present · IN

   Designed and executed pre-silicon performance validation for Intel\'s Granite Rapids and Sierra Forest server System on Chips, reducing debugging costs by 20% and accelerating time-to-market by 6 months.Developed and implemented comprehensive test plans, verification strategies for simulation and emulation environments, system bring-up, validation, automation to ensure delivery of best-in-class server SoCs.Developed an in-house performance validation infrastructure using Python for automated analysis, simulation, and performance KPI rollups, improving data post-processing, visualization, and debugging efficiency by 90%.Developed a performance validation framework to optimize Security Engine IP, enhancing bandwidth and resolving loaded latency issues, reducing silicon debugging time by 50% and accelerating time-to-market.Optimized SoC configurations with Architects, Firmware, BIOS, and Post-Silicon teams, boosting performance validation efficiency by 95% and improving production readiness for seamless deployment of server SoCs.Developed SystemVerilog and UVM-based verification stimuli, offering early architectural feedback to enhance performance, address potential issues early, and significantly reduce project timelines for faster delivery.Ramped up cross-functional teams by providing targeted training, sharing best practices, and offering technical guidance and mentorship, ensuring seamless collaboration, and accelerating validation timelines.Received the Award for Excellence in Performance Validation for resolving critical performance bottlenecks and driving high-quality validation across Granite Rapids and Sierra Forest server System on Chips (SoCs).

Education

• Chaitanya Bharathi Institute Of Technology

  B.E Electronics and Communication Engineering

• Indian Institute of Technology, Bombay

  Master of Technology - MTech

  2019 — 2021