Srividhya Devalingam
Design Verification Engineer at Capgemini Engineering
- Role
- Design Verification Engineer at Capgemini Engineering
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Srividhya Devalingam
Having 5+ years of experience in SOC Verification & strong knowledge in digital electronic, Verilog, System Verilog, UVM.
Experience
Design Verification Engineer
Nov 2022 — Present · Bengaluru, IN
Education
Government College of Engineering, Bargur
Bachelor of Engineering
2015 — 2019
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