Srivalli Kannappan
Physical Design Engineer @Eliyan Corporation
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WORK HISTORY
Physical Design Engineer @Eliyan Corporation
San Jose, CA, US
Implemented and achieved timing closure for 5 digital partitions (1M+ gates) at 2GHz across 3 tape-outs (2×TSMC 3nm, 1×Samsung 4nm). Executed full-chip and block-level STA using Tempus across 34 scenarios.• Eliminated 14.5µs setup and 30ns hold violations (100% closure) via constraint refinement, noise analysis, and manual ECO.• Performed CTS using CCOpt with clock balancing, shielding, and useful skew optimization in Cadence Innovus.• Collaborated with top-level integration teams to drive ECO convergence and ensure timing signoff readiness.• Developed a Git-based, YAML-configurable physical design flow for 35+ engineers, improving scalability and standardization.• Contributed to full power-grid architecture development at 3nm, defining synthesis-to-signoff implementation methodology.• Performed EMIR analysis using Voltus and resolved IR-drop and EM violations across all partitions.• Integrated Joules X-replay for enhanced power optimization and accurate estimation during synthesis and PnR, reducing power consumption by 25% on high-power partitions.• Reduced Chip Top DRC/LVS violations from∼20M to <200 using Cadence Pegasus and Virtuoso LVS, performing root-cause analysis to accelerate tape out readiness and prevent schedule risk.• Executed full-chip LEC and LVS/DRC closure for tape out readiness. Achieved signoff closure using Conformal LEC, Pegasus DRC/LVS, and Tempus STA, ensuring logical equivalence, physical correctness, and timing convergence for 3nm/4nm tapeouts. • Maintained technology collaterals and signoff methodology for advanced-node designs.
EDUCATION
Arizona State University
Master's degree, Electrical and Electronics Engineering
Anna University
Bachelor of Engineering - BE, Control and Instrumentation
ABOUT SRIVALLI KANNAPPAN
Currently a Physical Design Engineer at Eliyan Corporation, I implement complex digital partitions (1M+ gates) at 3nm and 4nm, achieving timing closure at 2GHz across multiple tape-outs. I contribute to advanced-node methodology development, full-chip CTS, power optimization using Joules X-replay, and signoff verification with Cadence Pegasus, Conformal, and Tempus STA. My work focuses on constraint refinement, ECO convergence, noise analysis, and ensuring logical and physical correctness for cutting-edge semiconductor designs. Previously, at NXP Semiconductors and Intel Corporation, I strengthened my expertise in STA, design automation, and visualization dashboards—improving flow efficiency and enabling scalable, high-quality design solutions. I thrive at the intersection of automation, high-performance design, and verification, leveraging tools such as Cadence Innovus, Synopsys Tempus, Voltus, and PrimeTime to deliver robust, optimized, and tapeout-ready silicon. I hold an M.S. in Electrical Engineering from Arizona State University and specialize in timing closure, advanced-node methodology, and automation-driven silicon design.
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