Sritharshinii R
VLSI Design | RTL Design and Verification | Verilog | System Verilog | UVM | Proactively looking for opportunities to contribute to the Semiconductor Industry
- Role
- Rtl Verfication at Rv Skills Design Centre
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EducationView LinkedIn profile
About Sritharshinii R
VLSI Design | RTL Design and Verification
Experience
Rtl Verfication
Jul 2024 — Present · Bengaluru, IN
Education
PSG College of Technology
Master of Engineering - VLSI Design
2022 — 2024
Government College of Technology, Coimbatore
B.E.,
2017 — 2021
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.