Srismrita Basu
Senior PTD Module Integration and Device Yield Engineer at Intel Corporation
- Role
- Senior Ptd Module and Integration Device Yield Engineer at Intel
- Location
- Hillsboro, OR, US
- LinkedIn followers
- 500 followers
About Srismrita Basu
Working on material characterization using Raman spectroscopy, AFM and SEM, thin film…
Experience
Senior Ptd Module and Integration Device Yield Engineer
Apr 2022 — Present · Hillsboro, OR, US
Responsible for planning and seamless processing of wafers through 18 Intel 4 and Intel 3 layers in the backend and Upper backend metals and vias printed on EUV, ASML immersion and Nikon immersion scanners with sustaining excellence. Working in a cross-functional team as process and tool expert to support yield impacting and cost improvement projects and meet the commit goal for new and active Intel products with high yield.Proficient at managing New Product Introduction for Intel’s advance technology nodes. Efficient in working at a high-pressure environment requires troubleshooting NPI issues in a time crunch manner.Recognized as Litho Process Quality Star for catching and correcting multiple quality issues during NPIs. Not only identified the issues each time but, contained and corrected the issue to prevent discrepant material from leaving the area.Experience in troubleshooting Litho process issues using SEM tools by conducting print test to identity reticle defects, in-die defect issues, exposure-focus process window mapping by writing SEM recipes and analyzing the data using statistical tools.Representing upper backend process team in various Focus Team meetings.Received Departmental award for saving 30hours of Engineering time per month by implementing Focus and Dose driven methodology in Intel 4 and 3 Backend and upper backend layer group.Recognized and was awarded DDA for outstanding support of multiple process change implementation in Intel 4 and 3 Backend and upper backend layer group.By doing data analysis using JMP, PCSA, and SPC I eliminated integrated risks such as CD, focus, dose-drifts & defect issues.Owned multiple Pro-v TEL tracks. Sustaining and development work to keep the tools up, robust and excursion free.Developed TEL track Recipes for cost reduction by reducing resists and solvent consumption and improving yields across 10 and 7nm process nodes. Owned the Track Resists InventoryTrained 20+ new Litho engineers in Litho
Education
University of Calcutta
Bachelor of Science (B.Sc.), Physics
2003 — 2006
West Bengal University of Technology, Kolkata
Master of Technology (M.Tech.), Electronics and communication engineering
2008 — 2010
University of Calcutta
Master of Science (M.Sc.), Electronics
2006 — 2008
Louisiana State University
Doctor of Philosophy (Ph.D.), Biomedical optoelectronics
2013 — 2017
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