Srishtansh Pathak

About Srishtansh Pathak

13 years of experience in VLSI Front-end Design & Verification - Leading UCIe PHY verification including test-plan, test bench from scratch, UPF, Gatesim, COSIM- presented “improved power aware mixed signal verification with UPF” at AMS SIG 2022- Successfully worked and owned and taped out HBM2e PHYIO verification and training/calibration- Exposure of Ams cosim, upf, reify- Lead and worked in DDR4 memory controller verification which includes component mode, UDIMM, RDIMM, LRDIMM and other configurations- Verification experience at both IP and SOC level - Verifying various Generic IP\'s in UVM and SV- Developing Testbench (UVM,SV)- Experience in developing all Testbench components from scratch (complex UVM env)- Coverage based verification, verification using SVA - Worked in verification of Memory controller like RLDRAM, DDR4- Worked in PHY-LAYER(serdes) verification used for multiple memory controllers- Worked in next gen DDR controller IP : HBM controller (High Bandwidth Memory Controller IP)- IP\'s like HMC- Controller (Hybrid Memory Cube Controller - serial serdes based memory), G722 (audio codec) etc- Clear understanding of object oriented programming concept and System Verilog- Worked on Generic Microcontroller based applications- Peripherals like Timer, PWM, bus system, AES etc- Excellent problem solving skills, good communication and interpersonal skills.

Experience

1. Senior Member of Technical Staff Smts

   AMD

   Jul 2025 — Present

Education

• CBSE

  HSC (Higher Secondary), Non-Medical

  2003

• Maharishi Markandeshwar University (MMU)

  Master of Technology (M.Tech.), Electrical, Electronics and Communications Engineering

  2009 — 2011

• Kurukshetra University

  Bachelor of Technology (B.Tech.), Electrical, Electronics and Communications Engineering

  2004 — 2007

Skills

• Vlsi
• Systemverilog
• Rtl Design
• Verilog
• Ncsim
• Verilog, Shell Scripting, Ovm, Systemc/Tlm 2.0