Sriram Varma Pericherla
Engineer - Analog Layout
- Role
- Analog Layout Engineer at MosChip®
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Sriram Varma Pericherla
Analog Layout Engineer | 2.5+ Years of Experience | CMOS, FinFET | Custom Layout | Cadence Virtuoso | Custom compiler Synapsys | DRC/LVS | IP & Full-Chip Design. Experience in Designed and developed for analog/mixed-signal layout for IP blocks including [e.g, ADCs, LDOs, Oscillators, Radios etc.] in TSMC6nm, TSMC7nm, UMC22nm, TSMC28nm, GPDK45nm, TSMC130nm, SCL180nm, TSMC180nm, Tower jazz 350nm technologies. Ensured the first-pass silicon success by following foundry guidelines and rigorous LVS/DRC/ERC checks. Supported successful tapeouts with full documentation and design sign-off.
Experience
Analog Layout Engineer
May 2023 — Present · Hyderabad, IN
Education
MosChip Academy of Silicon Systems and Technologies (MAST)
Analog layout
2022 — 2023
Srinivasa Institute of Engineering and Technology
Diploma
2018 — 2021
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.