Sriram D
Analog Layout Specialist | FINFET,GAAFET Expertise | Advanced Node Expertise (TSMC N7,N3) Other Tech Node (350nm,180nm,28nm,16nm,10nm,5nm) | High-Speed, Low-Power ICs | Senior Professional I @ Capgemini
- Role
- Analog Layout Design Engineer at Capgemini Engineering
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Sriram D
Overall 8 years of experience as a Analog Layout Design Engineer.Process / Technology experience in 350nm,180nm,28nm, 22nm, 10nm, tsmc7nm,intel7nm,intel 5nm (Ribbonfet)(18A), tsmc 3nm (finfet).Expertise in physical verification such as DRC/LVS/Antenna check, Latchup, EM/IR drop, density checks.Comprehensive exposure to floor plan, placement and routing in custom layouts.Interaction with client, handling the business queries and resolving it in earliest time.Holding Master degree in VLSI Design with First Class from CIT, Coimbatore.
Experience
Analog Layout Design Engineer
Jun 2017 — Present · Bengaluru, IN
Education
Tagore Engineering College
Bachelor of Engineering - BE, Electronics and Communications Engineering
2010 — 2014
Coimbatore Institute of Technology
Master's degree, vlsi design
2014 — 2016
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