Srinivasu Tammina
Soc Design Engineer @Intel
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WORK HISTORY
Soc Design Engineer @Intel
Bangalore Urban, IN
Memory Compiler Design & Characterization: Designed, validated, and optimized ROM and 1R1WRF compilers for low-power and low-leakage targets.Conducted comprehensive timing, power, and capacitance characterization based on a deep understanding of compiler architecture.Verification & Validation: Developed and validated Vmin test benches using Monte Carlo simulations to ensure robust read/write functionality.Executed critical validation checks, including timing ST pulse width, ERC, and noise violation assessments.Quality Assurance (QA): Spearheaded QA processes, including detailed trend/drift analysis and tight stimuli validation to ensure compiler robustness across all conditions
EDUCATION
Jawaharlal Nehru Technological University, Kakinada
Bachelor of Technology - BTech, Electronics and Communication Engineering
Indian Institute of Technology, Guwahati
Master of Technology (MTech), signal processing
ABOUT SRINIVASU TAMMINA
4+ years of industry experience in Memory circuit design and compiler IP validation and verification. I worked on different flavours of lower node (18A/5nm/7nm) ROM & RF compilers. Seeking challenging opportunities to work in leading memory products with high PPA targets.
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