Srinivasu Kamisetti

About Srinivasu Kamisetti

18 years of experience in Pre-silicon emulation, post silicon validation, and SOC functional verification domains for multiple AMD SOC products.• Experience in CPU/GPU based Firmware/OS/Driver bring up and debug using leading edge emulators (Veloce, Palladium, Zebu).• Experience in PowerOn/BIOS/OS/Driver/Power management/tools bring-up on post-silicon platforms.• Experience in working with Architects, SOC, IP, silicon validation, software and firmware teams to develop test plans and new emulation methodologies to achieve high quality BTO and silicon BU goals.• Design debug knowledge in SOC/x86 CPU/Fabric/Memory controller/power management/security/Reset/IO interfaces (PCIe, USB3, SPI etc.) in emulation.• SOC Debug experience using tools such as HDT software, Scan dumps, waveforms, Verdi, wave analyzer, VLA logs, gdb, debug scripts (JTAG/OS) and firmware traces.• Experience in emulation build infrastructure development and enablement on leading emulator platforms (Palladium/Veloce).• Experience in emulation-simulation based Accelerated testbench development and enablement to verify system-based SOC scenarios.• Experience in DDR Memory controller and PHY firmware validation of Client products using VCS based hybrid simulation environment.• Experience in Gate level netlist and power aware (UPF) design validation using BIOS/OS on emulator platform for Client NB products• Experience in SOC level verification of X86 based products and coverage closure using Detests in VCS simulation environment.• Silicon Engineering lead for Next Gen data center GPU MI SOC and responsible for test plan execution and driving debug forums to enable firmware/Software stack on both pre-silicon and post silicon platforms.• Pre-silicon technical lead for AMD Ryzen APU NB products and responsible for driving cross functional teams to align on project deliverables and validation of BIOS/OS/PMM stack on emulator.• Responsible for driving weekly convergence meetings with SOCDV/Doc/ Software model/Build/Firmware/Platform Emulation teams to track project milestone goals and deliverables to meet project TO/BU goals. • Responsible for presenting weekly Pre-silicon emulation status in program core team, SOC Ops meetings to project management team. • Provided technical leadership and mentorship to junior engineers in the team and helped them to improve SOC design debug knowledge and firmware debug skills. Successfully implemented process optimizations that enhanced efficiency and reduced time-to-market for critical deliverables.

Experience

1. Pmts Systems Design Engineer

   AMD

   Nov 2007 — Present · Austin, TX, US

   Current role: Silicon Engineering lead for AI-Datacenter GPU server product.Past roles:Pre-silicon emulation debug lead for client Notebook APU productsSOC level Pre-silicon/Post silicon debug expert for power on/BIOS/FW/OS/driver/design related issuesEmulation model lead for building and infrastructure development for multiple APU productsSOC level verification lead and debug expert for multiple AMD CPU products.

Education

• Jawaharlal Nehru Technological University

  M.Tech

  2003 — 2005

• Jawaharlal Nehru Technological University

  B.Tech

  1999 — 2003

Skills

• Debugging
• Perl
• X86
• Emulation
• Vmm
• Functional Verification
• Systemverilog
• Asic
• Rtl Design
• Verilog
• Vlsi
• Processors