Srinivasa S S

About Srinivasa S S

Over 14+ years of experience in Front End Digital Design & Digital IP Development and Directed VerificationDomain Knowledge-• Good understanding on networking domain like L2 Ethernet controllers, L3 IP and L4 Layers TCP/UDP offload controllers like TSO(Transmit Segmentation Offload), COE (Checksum Offload Engines), LRO (Large Receive Offload), RSS (Receive Side Scaling), ARP, ICMP• Good Understanding of Virtualization Protocols like VxLAN and NVGRE• Implementation Details of Ethernet PCS Layer Protocols Like SGMII(1G PCS/KX), XAUI(10G PCS KX4), KR(10G PCS), KR4(40G PCS) and 100G PCS, Clause 73 Auto-negotiation and Clause 72 Training, • KR FEC (KR Forward Error Correction), 8b/10b, 64/66b encoding, Scrambling, De-scrambling, Gear Box Designs, Clock Rate Compensation etc.• Ethernet 1G/10G/40G MAC protocols (GMII, XGMII, XLGMII, Pause Flow Control, efficient Ethernet), CRC Generation/Checking, RMON Counters, VLAN, Routing based on L2//L3//L4 addresses, RSS hashing).• DCB (Data Center Bridging Protocols) like PFC (Priority Based Flow Control), ETS Scheduling Algorithms (DWRR, WFQ, WRR)• Prior Experience in working on USB and ATA/ATAPI and Nand-Flash Storage Controllers• Extensive experience in Complex FIFO controller Designs and Scatter Gather DMA controller Designs• Good knowledge of AMBA AXI protocol-Skills-* Digital Design, Functional Spec Development, Architecture and Micro Architecture Developement and Implementation using Verilog RTL * Very Good Understanding on CDC, Lint, GLS* Directed Verification experience, Knowledge of using VIPs and Very good debugging skills* Hardware Debugging/Post Silicon Validation knowledge and experience. Familiar with FPGA/ASIC Flows-

Experience

1. Senior Principal Engineer

   Marvell Technology

   Oct 2023 — Present · Bengaluru, IN

Skills

• Functional Verification
• Static Timing Analysis
• Systemverilog
• Verilog
• Soc
• Fpga
• Asic
• Rtl Design
• Vlsi
• System on a Chip (Soc)