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Srinivas Parla

Analog layout, Tech Lead at Intel

Role
Analog Layout at Intel
Location
Hyderabad, TG, IN
LinkedIn followers
500 followers
EngineeringView LinkedIn profile

Experience

  1. Analog Layout

    Intel

    Sep 2016 — Present · Bengaluru, IN

Education

  • BITS Pilani

    M.E

    2010 — 2012

Skills

  • Asic
  • Pll
  • Physical Verification
  • Vlsi
  • Physical Design
  • Cadence Virtuoso
  • Cmos
  • Floorplanning
  • Static Timing Analysis
  • Lvs
  • Ic
  • Drc

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Srinivas Parla — Analog Layout at Intel in Hyderabad, TG, IN | Unifers