Srinidhi Nagaraj
- Role
- Sr Director, Rtl Integration and Physical Design at AMD
- Location
- Santa Clara, CA, US
- LinkedIn followers
- 500 followers
Experience
Sr Director, Rtl Integration and Physical Design
Jul 2023 — Present
Skills
- Floorplanning
- Physical Verification
- Rtl Design
- Static Timing Analysis
- Place & Route
- Logic Synthesis
- Fpga
- Integrated Circuit Design
- Lvs
- Logic Design
- Debugging
- Dft
- Processors
- Microprocessors
- Physical Design
- Eda
- Soc
- Low-Power Design
- Drc
- Hardware Architecture
- Engineering Management
- Verilog
- Ic
- Formal Verification
- Vlsi
- Cmos
- System on a Chip (Soc)
- Mixed Signal
- Functional Verification
- Primetime
- Timing Closure
- Tcl
- Systemverilog
- Asic
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