Srinath Ramini
VLSI DV ENGINEER | SOC/IP Verification | ETHERNET,AXI, APB Protocols | VERILOG,SV,UVM | Python | Gvim |
- Role
- Engineer at Truechip
- Location
- Hyderabad, IN
- LinkedIn followers
- 500 followers
About Srinath Ramini
Title: Design Verification EngineerSummary:As a passionate and detail-oriented Design Verification Engineer with 1.7 years of industry experience, I am dedicated to ensuring the reliability and functionality of complex digital designs. My journey in the world of semiconductor design has allowed me to work on diverse projects, contributing to the success of cutting-edge technologies.My skills and expertise include:Test-bench development and simulation using industry-standard tools such as System Verilog and UVM.Scripting and automation with languages like Python for improved verification efficiency.Analyzing and debugging complex digital systems to ensure optimal performance.Collaborating with cross-functional teams to meet project goals and deadlines.I thrive on solving intricate problems, diving deep into verification challenges, and ensuring that designs are robust and error-free. My commitment to continuous learning in this ever-evolving field enables me to stay at the forefront of verification methodologies and best practices.I am excited to connect with fellow professionals, share insights, and explore opportunities to contribute to innovative projects in the semiconductor industry. Let\'s connect and discuss how my skills and experience can add value to your organization.
Experience
Engineer
Jul 2024 — Present · IN
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.