Srinand Venkatesan
Director of Engineering @Intel
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WORK HISTORY
Director of Engineering @Intel
Delivered high-quality A0 silicon for Intel’s first PCIe-G6/CXL3.0 Endpoint device while leading a global team of 30+, managing all aspects of Pre-Silicon Execution, and presenting monthly updates to VP-level executives.Provided effective leadership in a highly cross-matrixed environment, through Stakeholder Management, clear communication and decision making, to 16-member Arch/Design team, including 4 Principal Engineers, resulting in timely delivery of the Architecture Specifications and DFx features for PCIe5/CXL1.0/UPI IO Stack and Acceleration sub-systems, enabling robust HVM testing and productization of a very competitive design across 12 SKUS and 3 steppings of Intel Xeon 6 (Granite Rapids) Processor.Provided effective Engineering Management leadership, to a 25+ member global team, ensuring timely delivery of Arch definition in multiple sub-system areas, such as Reset, Clocking, ARM compute complex as well as delivery of DFT features for 3 complex sub-systems resulting in contributing to the successful launch of the Mt Evans IPU product.Led a Global DFT Team (US, Malaysia) in implementing/validating DFT features, including Scan, MBIST and Tap for QAT/Hardware Queue Manager Sub-systems, enabling robust HVM testing and productization across 23 SKUS and 4 steppings of two Multi Core Count Die variations of the 4th-Gen Xeon Server/Workstation CPU.Led a 25+ member Global SoC Structural Design Team (US, Malaysia) to successfully deliver 6 steppings of two generations of Intel Optane Persistent Memory Controller (Apache Pass and Barlow Pass) and 2 steppings of the Lewisburg chipset for the Skylake Xeon CPU.
EDUCATION
Bangalore University
Bachelor's Degree
The University of Texas at Austin
Master's Degree
ABOUT SRINAND VENKATESAN
Director/Sr. Engineering Manager at Intel
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