Sriman T
Lead Design Engineer at Cadence Design Systems | VLSI | Design Verification
- Role
- Lead Design Engineer at Cadence
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Sriman T
Hi,I am Sriman T, completed my B.E(ECE) Degree at Anand Institute of Higher Technology, specializing in VLSI Digital Design and verification and I am looking for an Co-op position for VLSI industry.Over the years I have garnered academic and industrial experience to refine my skills and learn in various fields. I believe in continuous and diversified learning and love challenging projects.My areas of interest include RTL design, verification, SOC and ASIC design.VLSI DOMAIN SKILLS-Hardware Description Languages:Verilog, System Verilog for verification-Verification Methodologies: Coverage Driven Verification, Assertion Based Verification - SVA -TestBench Methodology: UVM (Universal Verification Methodology)-Scripting Language:Perl,shell, python -EDA Tool: Questasim, Xilinx ISE, Rivera Pro, EDA Playground, VCS, Xelieum -Domain: ASIC/FPGA front-end Design and Verification -Operating System: Linux, Windows. CERTEFICATIONS/PROFESSIONAL TRAININGS:Advanced VLSI Design and Verification course from Maven Silicon VLSI Design and Training Center, Bangalore, India.[June 2017 – Jan 2018]Email: t••••••••@gmail.com
Experience
Lead Design Engineer
Jun 2022 — Present · Bengaluru, IN
Education
Anand Institute Of Higher Technology
Bachelor's degree, Electrical, Electronic and Communications Engineering Technology/Technician
2013 — 2017
Tagore higher secondary school, salem
Mathematics and Computer Science
2008 — 2013
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